Metal-oxide-semiconductor ("MOS") electrically programmable read-only memories ("EPROMs") frequently use memory cells that have electrically isolated gates (i.e., floating gates). Information is stored in the memory cells in the form of charge on the floating gates.
One type of prior EPROM is the flash erasable and electrically programmable read-only memory ("flash EPROM"). The flash EPROM can be programmed by a user, and once programmed, the flash EPROM retains its data until erased. Once programmed, the contents of the flash EPROM can be erased by electrical erasure. The flash EPROM may then be reprogrammed with new codes or data.
The flash EPROM typically includes a plurality of normal operating modes. Those normal operating modes include read modes, write modes, and a standby mode. For a read mode, a logical low signal is applied to both the chip enable pin CE and the output enable pin OE. This permits data stored in the flash EPROM to be read out as addressed. Addresses are provided at the address pins to access the data stored in the memory array.
A write mode allows device erasure and programming in the flash EPROM. Operation of the flash EPROM in the write mode also includes the read operation. The flash EPROM enters into the write mode by applying a 12 volt high voltage to the Vpp pin of the flash EPROM and a logical low voltage at the write enable pin WE while the chip enable pin CE is at logical low level. Operations of the flash EPROM, such as read, program or erase, are selected by writing specific commands into its command register at the write enable signal WE. The commands typically include the erase command, the erase verify command, the program command, the program verify command, and the read command. When the 12 volt high voltage is removed from the Vpp pin of the flash EPROM, the content of the command register defaults to the read command, making the flash EPROM a read-only memory.
A standby mode is entered by applying a Vcc high voltage at the chip enable pin CE of the device. Power consumption of the flash EPROM is substantially reduced in the standby mode.
One disadvantage of this prior flash EPROM is that the flash EPROM still consumes a certain amount of power in the standby mode. One reason is that some circuits in the flash EPROM need to be or are powered during the standby mode. For example, the bias circuit for content addressable memory ("CAM") cells in the flash EPROM is maintained fully powered during the standby mode. The flash EPROM typically includes CAM cells in addition to the main memory array. The CAM cells can be programmed to configure the memory device operation (for example, latched inputs, CEBTTL active high, and OEBTTL active high). The CAM cells can also be used to activate (or deactivate) redundancy cells with respect to the main memory array. The redundancy cells are used in place of defective cells of the main memory array.
Another circuit in the flash EPROM that needs to be powered in the standby mode is the Vcc voltage detector. The Vcc voltage detector needs to be constantly fully powered in order to detect a low Vcc condition at any time.
In one prior flash EPROM, the memory array can store data and program code. A separate flash memory may, for example, be used to store boot code. The boot code can be program code for system initialization and reprogramming, for example. Boot code typically requires minimal updating.
One disadvantage of the above way of storing boot code is that at least two memories are required--one to store the boot code, and the other to store other program code and data--in order to avoid inadvertent erasure or programming of the boot code. Inadvertent erasure or programming of the boot code has the potential for rendering an entire computer system nonfunctional.